library ieee;
use ieee.std_logic_1164.all;

entity counterBlockTb is
end entity counterBlockTb;
architecture RTL of counterBlockTb is
	
signal enIn, clrIn, clkIn : bit;
signal result : bit;
	
component counterBlock
	
	port (en, clr, clk: in bit;
		output : out bit
	);
	
	
end component;

	for all : counterBlock use entity work.counterBlock(STRUCTURAL); 
	
begin

	COUNTER : counterBlock port map (
		enIn, clrIn, clkIn, result	
	);

	clkIn <= not clkIn after 10 ns;

	tb : PROCESS
		
	begin
	

	
	enIn <= '0';
	clrIn <= '0';

	wait for 20 ns;
	enIn <= '1';
	wait for 4000 ns;
	enIn <= '0';
	wait for 20 ns;
	clrIn <= '1';
	wait for 20 ns;
	enIn <= '1';
	wait for 400 ns;
	clrIn <= '0';
	wait for 80 ns;
	
	wait;
		
	end PROCESS;

end architecture RTL;

